Switched-capacitors are commonly used to approximate resistors in signal processing integrated circuits. Using switched-capacitors as resistors provides several advantages. For example, switched-capacitors generally require less surface area on an integrated circuit than a resistor having an equivalent value, and switched-capacitors provide greater accuracy than resistors. The greater accuracy is possible since the resistance of the switched-capacitor circuits depends on the ratio of the capacitance values, and not on the actual sizes of the capacitors.
In filter circuits using switched-capacitors, a clock is used to provide nonoverlapping clock signals to control the sampling of an input signal. The sampling frequency should be much greater than the frequency of the sampled input signal, and the capacitors of the filter circuit, including any parasitic capacitance, are charged and discharged at the appropriate switching time. During recharging of the capacitors, the output signal of the filter may not be at the required voltage. If the output signal is used as a continuous time output, then the output signal is in error during the time it is settling. This error may appear as a "glitch" on the output signal. If the input signal is over-sampled, the average error, or glitch, from recharging the capacitors, can be significant.
FIG. 1 illustrates in schematic diagram form, prior art switched-capacitor biquad filter 10. Switched-capacitor biquad filter 10 includes first stage 11, second stage 20, and feedback switch 33. First stage 11 includes operational amplifier 12, switches 13, 15, and 16, and capacitors 14 and 17. Second stage 20 includes switched-capacitor circuit 21, operational amplifier 28, switches 30 and 31, and capacitors 29 and 32. Switched-capacitor circuit 21 includes switches 22, 24, 26, and 27, and capacitor 23. Switches 16, 22, 27, and 31 receive a clock signal labeled ".phi.1", and switches 13, 15, 26, 24, and 30 receive a clock signal labeled ".phi.2". Clock signals .phi.1 and .phi.2 are out-of-phase non-overlapping clock signals, such that when .phi.1 is active, .phi.2 is inactive. Note that a fully differential configuration of switched-capacitor biquad filter 10 may be constructed by replacing operational amplifiers 12 and 28 with operational amplifiers having differential input terminals and differential output terminals, and repeating the other circuitry shown in FIG. 1.
Switch 13 has an input terminal for receiving an input signal labeled "V.sub.IN ", and an output terminal connected to capacitor 14. Switch 16 and capacitor 17 are connected in series between an input terminal and an output terminal of operational amplifier 12. Switch 15 provides an auto-zero function for switched-capacitor biquad filter 10 which increases steady state accuracy.
Switched-capacitor biquad filter 10 functions as a unity gain low pass filter, with a very precise unity gain transfer function. Switched-capacitor biquad filter 10 has a precise unity gain transfer function because capacitor 14 senses both the input signal V.sub.IN, and the output signal V.sub.OUT through a feedback signal path to the first plate electrode of capacitor 14. This eliminates matching errors and provides a DC transfer function that is exactly unity.
The problem with switched-capacitor biquad filter 10 occurs when output signal V.sub.OUT is sensed in continuous time. When a continuous time output is required, output signal V.sub.OUT is best described in the Laplace (s) domain instead of the discrete time (z) domain. Any non-linear movement of output signal V.sub.OUT, which is correlated with the input signal V.sub.IN, causes distortion in output signal V.sub.OUT. When switch 31 is open, a charge may accumulate on the parasitic capacitance of the common node between switch 31, capacitor 29, and switch 30. When switch 31 is closed, the parasitic capacitance is discharged to V.sub.AG. When switch 31 reopens and switch 30 closes, operational amplifier 28 must recharge the parasitic capacitance. Charging of the parasitic capacitance by operational amplifier 28 causes operational amplifier 28 to slew rate limit. Slew rate limit is a non-linear effect and therefore causes distortion.
Any parasitic capacitance coupled to the output terminal of operational amplifier 12 is discharged to V.sub.AG when switch 15 is closed. Operational amplifier 12 also slew rate limits when it charges the parasitic capacitance coupled to its output terminal. When switch 15 is open, switches 16 and 33 are closed, thus coupling the output terminal of operational amplifier 28 to the output terminal of operational amplifier 12 via capacitor 17, switch 16, capacitor 14 and switch 33. Output signal V.sub.OUT is adversely affected by the nonlinear recovery of operational amplifier 12, which causes distortion in output signal V.sub.OUT.